ASIC DFT
Several opening positions for ASIC DFT at Cisco, from senior engineering level to technical leader level, are available. If you are interested in these positions.
Layout Engineer
We are looking for experienced layout engineers. Interested professionals, please contact at www.piconetics.com
Design Engineer
Location:
Contact- Subject: Electrical Engineering (Research)
Our group (Circuit Research Lab), located in OR & a part of MRL
(Microprocessor Research)/CTG, has an opening for a design engineer with the
following requirements.
Candidate will be part of a design team to learn and develop advanced design
techniques and methodologies to be deployed for future Intel products. The job
involves working with technology research and development team to build
prototype components on the leading edge design processes. Responsibilities
include micro-architecture, RTL modeling, architecture and logic simulations,
circuit design, synthesis and performance verification, chip planning, layout
supervision, design validation and test development in a VLSI component design
environment. Background in VLSI design is a must. Good programming
Product Characterization (Advanced
Analogic Tech)
Location: Sunnyvale, CA
Contact
Description: Qualification:
A pre-IPO Analog semiconductor company. This
company is a fab-less company designs power management chips.
The position is for doing product characterization, yield enhancement, and new
product introduction.
BSEE or BS Physics.
R&D Photolithographic Engineer (Cypress
Semiconductor) Description: A new engineer (if you've already graduated, or will graduate in
the near future) in an R&D photolithography position. Qualification: Experience with lithography and semiconductors, as well as
some background in semiconductor device physics, is desirable.
Location: San Jose, CA
Contact -
Job posted: Aug 11, 2004
Senior position in high-speed device
Characterization (Altera) Qualification:
Location: San Jose, CA
Contact - Subject: Job #135
A PhD qualification is preferred. The candidate
should have in-depth knowledge in signal-integrity, device, package (BGA) and
PCB modeling for noise (SSN) and power integrity analysis. Circuit and
architectural knowledge of analog blocks such as PLL, Clock Data Recovery and
high-speed buffers are also required. The position will involve working with lab
equipment and simulation software. The candidate must have excellent written and
oral communication skills. Knowledge in specific high-speed protocols such as
XUAI and Giga-bit Ethernet is a plus but not required.
Product Management (Oracle) Qualification: Product management experience.
Location: Bay Area, CA
Contact -
Wafer Inspection Products Support (KLA-Tencor) Description: Qualification:
Location: San Jose, CA
Contact -
Responsible for supporting wafer inspection products. The job
functions Include tasks and projects related to: (1) new product introduction
such as characterization, alpha and beta testing and pilot support in the ramp
phase; (2) managing in-house customer demonstrations and competitive activities
at customer facilities; (3) generating best known method documents and other
training material and transferring product knowledge to worldwide Field
Applications teams; (4) working with customers to publish papers at industry
symposiums or technical journals.
Work closely with internal teams including applications, engineering, sales and
marketing as well as with customers outside the company.
Domestic and international travels (on average 25%) will be required to support
company?s inspection products at customer fabs.
Candidate must hold either the BS, MS or Ph.D. degree in
Engineering, Physics, Chemistry, Material Science or related fields. Having a
background in IC processing/Semiconductor physics is a plus. Must have excellent
communication, organizational, analytical, leadership, and interpersonal skill.
Candidate must also be self-driven, yet a strong team player.
Sr. Process Engineers (Intel) Description: Qualification:
Location: Portland, Oregon
Several positions for senior process engineers in the
lithography group. If you graduate this May or graduated less than a year (PhD),
please contact with subject: Job #138.
Lithography and device physics knowledge and experience.
Sr. ASIC designer Qualification:
Contact: calshu@sbcglobal.net
Senior ASIC designers with experiences in all aspects of
RTL design flow from specification/architecture definition to design and
verification.
Some familiarity with ATA/SCSI protocols desirable.
Sr. circuit/logic designer Senior circuit/logic designers with experiences in high-speed custom data
path logic and circuit design and layout supervision in deep-submicron CMOS
processes. Interested professionals, please email to
calshu@sbcglobal.net
Project Lead/Manager Project Lead/Manager with hands-on experiences in all phases of complex IC
development projects.
Contact: calshu@sbcglobal.net
Responsibilities include team-building, design
infrastructure/process setup and management of design/verification
activities/team.
High-speed analog circuit designer We are looking for high-speed analog circuit designers with experiences in
ADC, synthesizer/PLL, and continuous-time filter. To apply for this position,
please send your resume to
calshu@sbcglobal.net
Engineering Supervisor Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
Manage the Applications Support Group, which is responsible
for the following tasks: Writing product data sheets, application notes, Sales/FAE
training and supporting Exar's Network and Transmission customers.
BSEE required/MSEE desired plus 3 years of applications
support experience and 5 years of hardware design experience. Must possess good
verbal and written communication skills.
Staff Test Engineer Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
Staff level test development engineering capable of
developing independently, production worthy, robust hardware and software test
solutions for a variety of mixed signal devices such as LIU's, framers, mappers,
transceivers, etc., on automatic test equipments such as Agilent (93000) and
Teradyne (A5XX).
The qualified candidate should have a BSEE or MSEE, with
at least 6-8 years of hands on test development experience with mixed signal
devices. Good working knowledge of Agilent 93000 series is required. Exposure to
high pin count devices, high frequency testing and signal integrity issues are
required. Working knowledge of Teradyne mixed signal testers is desirable.
Working knowledge of Vtran, C and C++ is desirable. Should be a self-starter,
capable of managing several products, with good oral and written communication
skills.
Sr. Applications Engineer Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
Provide technical support for PLL clock generators and Clock
distribution devices. Write Application Notes, Data Sheets and White Papers for
clock products. Design and develop evaluation boards and characterize new clock
products.
Requires a BSEE or equivalent and 5+ years of
experience. (MSEE preferred). Proficiency in the use of laboratory test
equipment, a good background in system design in a mixed analog and digital
environment for high speed computer or telecom equipment, familiarity with
signal integrity and PCB layout issues, knowledge of clock characteristics (e.g.
jitter specifications), and excellent verbal and written communication skills
are required. Experience with IBIS, Spice, Lab VIEW is desired.
Strategic Marketing Manager I Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
This position will define the product marketing
requirements for wire-line communications IC products for Access and Metro
markets, as well as for Storage IC markets. Will be responsible for marketing
strategies, forecasts and new product concepts, and will determine product life
cycle strategy, product migration and engineering priorities. Must be proficient
at tracking competition and industry trends in wire-line communications as well
as Storage markets, and transforming market needs to well-defined and detailed
product specifications. This position is expected to succeed in securing a high
number of design wins, and is responsible for providing all the required
collateral for product support such as data sheets, product briefs and reference
designs.
BSEE plus 4 years of experience, or MSEE plus 2 years of
experience required. MBA is desired. This position requires a broad
understanding of analog/digital design and marketing/engineering concepts for
wire-line communications applications including Storage applications, next
generation I/O technology (such as PCI express) and/or SONET/SDH. Ideal
candidate will have experience in dealing with multiple customers and will have
good verbal and written communication skills.
Sr. Staff Design Engineer Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
This position will develop the Ethernet Aggregator product
line. Candidate must be thoroughly familiar with both WAN & LAN protocols and
possess very strong skills to lead a team to complete SOC development from
Definition to Production.
MSEE with 8+ years of related industry experience
required. Candidate must have strong logic & digital design skills using Verilog
as well as experience with Synopsys tools for DC, DFT, ATPG. Experience with
Unix & C, as well as strong Ethernet and SONET background a plus.
Design Engineer Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
This position will develop Ethernet Aggregator products.
Candidate will be responsible for the design, verification, synthesis and
testing of System-On-Chip type of IC's.
MSEE with 0-5 years of industry experience, and knowledge
of digital and logic design required. Familiarity/experience with Unix systems
and C programming, Synopsys tools, DC, DFT, and knowledge of Telecom/Ethernet
technologies desired.
Sr. Staff Firmware Engineer Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
Responsible for all aspect of embedded software development
for system communication protocol based on microcontroller architecture, in
cooperation with the hardware design team.
The qualified candidate must have a successful track
record of embedded communication data packet routing protocol development with
microcontroller in C and assembly languages from concept to product delivery.
Require BS or MS in EE or Computer Engineering equivalent plus 8+ years of
embedded firmware design, development, debugging, optimizing, and testing
experience. Proficient in C, assembly language, and knowledge of software
engineering principles. Must be self-motivated, self-directed, and have
demonstrated ability to work well with people. A proven desire to work as a team
member, both on the same team and outside of the team. Ability to be creative,
troubleshoot and analyze complex problems, and to multi-task and meet deadlines.
Excellent communication (written and verbal) and interpersonal skills.
Sr. Engineering Manager Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
Exar is seeking a hands-on Design Manager or Technical Lead
for System-On-Chip (SOC) product development. The successful candidate will have
the opportunity to contribute in all phases of the design process. Will provide
leadership in architectural definition, detailed block and chip design
specification, HDL coding and synthesis, simulation, place and route oversight,
timing closure, and validation, in cooperation with other engineers from various
disciplines, to assure the functionality and testability of the designs. Will be
required to support product and test engineering teams with production test
program development, characterization, qualification and release to production
activities. Must be able to participate in technical discussions to support
customers.
BSEE or MSEE with 8+ years of SOC/ASIC design experience,
strong knowledge of SOC design methodologies, and some managerial experience is
a plus. The candidate should have participated in several design cycles for
medium size SOC designs. This position requires the understanding of CMOS
design, tape out flows and extensive experience with design and verification
tools. Must be fluent in HDL coding, preferably Verilog, VHDL a plus. Experience
in Synthesis (Synopsys Design Compiler), Static Timing Analysis (PrimeTime),
behavioral modeling and verification, and Design for Test (DFT) is required.
Knowledge of Automated Place and Route, extraction and physical design is a
strong plus. Must possess strong analytical skills and be familiar with modern
tool flows. Knowledge in UNIX, C/C++, Perl/TCL/shell scripting required.
Experience with embedded Flash technology, microcontrollers and FPGA design is
useful. Ideal candidate will be self-motivated, self-directed, and have
demonstrated ability to work well with people, and a proven desire to work as a
team member. Will also possess the ability to troubleshoot and analyze complex
problems, and to multi-task and meet deadlines. Excellent communication (written
and verbal) and interpersonal skills a must.
Northern Europe Sales Manager Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: UK (home office or business center)
Drive growth strategiy including reaching or exceeding
booking/billings/design wins targets through the Northern Europe region.
Worldwide Account Management of Ericsson, Nokia and Marconi. Pan-European
distributor coordination role and Local distribution channel management.
Consolidate and clearly report via company tools the booking forecast and design
opportunities status on a monthly basis.
BScEE plus 10 years experience in semiconductor servicing
broadband access and transport communications markets in the Northern Europe
region. Intimate knowledge of Ericsson, Nokia and Marconi. Proven track record
of success in account management and regional sales management. Effective
communicator at all levels within Key Accounts and Exar. Ability to work
independently in a remote location. Fluent in English (Swedish or Finish is a
plus).
Sr. Inside Sales Representative Description: Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
Develop contacts with reps., customers and distributors to
understand their business needs; Manage order processing, sample requests and
backlog for a designated U.S. sales region; Provide inside interface and support
for pricing, agreements, and delivery of products; Participate in bookings
forecasts and development of sales leads.
BS plus 5-7 years of inside sales / customer service
experience in the Semiconductor industry; Minimum of 3 years inside sales
experience managing a large U.S. geographical region; Familiarity with Order
Entry Management software packages such as Oracle as well as Microsoft Office.
CAE / Sr. CAE Engineer Description: >Qualifications: Interested professionals, please email to
calshu@sbcglobal.net
Location: Fremont, CA
Responsible for the development and support of design tools,
libraries and technology for both digital and analog designs. Includes
schematics, simulation (SPICE and Verilog), synthesis, layout and P&R.
Engineering Degree (BS/MS) plus 3 to 5 years experience
in an IC CAD tool environment. Knowledge of a Cadence DFII environment;
Knowledge of basic digital tools (Synthesis, Verilog, Timing); Knowledge of
analog design tools (HSpice, Virtuoso); and Knowledge of programming in Skill,
Perl and C required.
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